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- 1 - prm48bh480 x 250a00 rev. 1.0 11/2012 prm? regulator features ? 48v ? input ? (38v ? to ? 55v), ? non \ isolated ? zvs ? buck \ boost ? regulator ? ? 20v ? to ? 55v ? adjustable ? output ? range ? ? 250w ? output ? power ? in ? 0.57in 2 ? footprint ? ? 96.7% ? typical ? efficiency, ? at ? full ? load ? ? 1670 ? w/in 3 ? (102 ? w/cm 3 ) ? power ? density ? ? 5.28 ? mhrs ? mtbf ? (mil \ hdbk \ 217plus ? parts ? count) ?? ? pin ? selectable ? operating ? mode ?? ? adaptive ? loop ?? ? remote ? sense ? / ? slave ?? ? half ? vichip ? package ? ? 22.0mm ? x ? 16.5mm ? x ? 6.73mm ? typical applications ? high density power supply dc-dc rail outputs ? high density ate system dc-dc power ? telecom npu and asic core power ? communications systems ? non-isolated and isolat ed power converters description the vichip? prm? regulator is a high efficiency converter, operating from a 38 to 55 vdc input to generate a regulated 20 to 55 vdc output. the zvs buck ? boost topology enables high switching frequency (~1.03 mhz) operation with high conversion efficiency. high switching fr equency reduces the size of reactive components enabling power density up to 1670 w/in 3 . the half vichip package is compatible with standard pick -and-place and surface mount assembly processes with a planar thermal interface area and superior thermal conductivity. in a factorized power architecture? system, the prm and down stream vtm? current multiplier minimize distribution and conversion losses in a high power solution, pr oviding an isolated, regulated output voltage. the prm48bh480[x]250a00 has two selectable modes of regulation depending on the application requirements. in adaptive loop operation, t he prm48bh480[x]250a00 utilizes a unique feed-forward scheme t hat enables precise regulation of an isolated pol voltage without the need fo r remote sensing and voltage feedback. in remote sense operation, the internal regulation circuitry is disabled, and an external control loop and current sensor maintain regulation. this affords flexibility in the design of both voltage and current com pensation loops to optimize performance in the end application. product ratings v in = 38v to 55v p out = 250w v out = 48v (20v to 55v trim) i out = 5.21a
- 2 - prm48bh480 x 250a00 rev. 1.0 11/2012 typical applications typical application: prm48bh480[x]250a00 + vtm adaptive loop configuration typical application: prm48bh480[x]250a00 + vtm non-isolated remote sense configuration [1] non-isolated configuration: ?out connected to -in vt m st art up pul se adaptive loop temperature feedback 36v to 75v vf: 20v to 55v lf ral rtrim cf cout cin sgnd sgnd gnd on/off control vin vout sec_gnd trim al +in -in +out -out vc ifb vt ref/ ref_en vaux share/ control node enable sgnd prm sgnd +in -in +out - out vc pc primary secondary isol at ion boundry tm vtm cf cin 36v to 75v cout lf voltage reference with soft start v+ vout +in v- -in voltage sense and error amplifier voltage sense (single ended) external current sense and feedback in out gnd sgnd on/off control vin sgnd sgnd sgnd sgnd gnd gnd vout vtm startup pulse vref trim al +in -in +out -out vc ifb vt ref/ ref_en vau x share/ control node enable sgnd prm sgnd +in -in +out -out vc pc primary secondary isol at ion boundry tm vtm [ 1 ] [ 1 ] v in 38v to 55v v in 38v to 55v
- 3 - prm48bh480 x 250a00 rev. 1.0 11/2012 pin configuration pin descriptions pin signal name type function number a1 share (adaptive loop / slave operation) bidir parallel sharing control bus for master-slave configuration. control node (remote sense operation) input modulator control node input. driven by external error amplifier in remote sense operation. a3 vt (adaptive loop operation) input vtm tm input for temperature compensation. leave disconnected for remote sense operation. b2 enable bidir enables power supply when allowed to float high. 5.0v during normal operation. b4 vaux output 9.0v auxiliary bias voltage. c1 trim input selects operating mode. adjusts output voltage in adaptive loop operation. c3 ifb (remote sense operation) input current sense input for current limit and overcurrent protection in remote sense operation. leave disconnected for adaptive loop operation. d2 nc n/a do not connect this pin. d4 sgnd input signal ground, reference for analog controls. kelvin connected internally to ?in and -out. e1 nc n/a do not connect this pin. e3 ref (adaptive loop operation) output reference voltage for internal error amplifier in adaptive loop operation. ref_en (remote sense operation) output powers and enables external control circuit voltage reference in remote sense operation. f2 al (adaptive loop operation) input adaptive loop gain control. sets the magnitude of the adaptive loop load line in adaptive loop operation. leave disconnected for remote sense operation. f4 vc output bias voltage to power vtm module during start up g1,g2 +in input power positive input power terminal g3,g4 +out output power positive output power terminal h1,h2 -in input power return negative input power terminal. connected internally to ?out. h3,h4 -out output power return negative output power terminal. connected internally to -in.
- 4 - prm48bh480 x 250a00 rev. 1.0 11/2012 part ordering information part ordering information device type input voltage range package type output voltage x 10 temperature grade output power revision version prm 48b h 480 t 250 a 00 prm = prm 48b = 38v ? 55v h = half vic smd 480 = 48v t = -40 to 125 c m = -55 to 125 c 250 = 250w a 00 = al / rs standard models part number vin package type vout temperature power version prm48bh480 t 250a00 38v ? 55v half vic smd 48v (20v to 55v) -40 to 125 c 250w al / rs (pin selectable) prm48bh480 m 250a00 -55 to 125 c
- 5 - prm48bh480 x 250a00 rev. 1.0 11/2012 absolute maximum ratings the absolute maximum ratings below are stress ratings only. operation at or bey ond these maximum ratings can cause permanent damage to device. electrical specifications do not apply when operating beyond rated operating conditions. operating beyond rated operating conditions for extended period of time ma y affect device reliability. all voltages are specif ied relative to sgnd unless otherwise not ed. positive pin current represents current flowing out of the pin. absolute maximum ratings parameter comments min max unit share / control node ???????????????????????????.................................................................................................... ....................................... -0.3 10.5 v +/- 10 ma enable ???????????????????????????............................................................................................. .............................................. -0.3 5.5 v +/- 10 ma +in to ?in continuous, non-operating ..................................................................................................... .......................................................................................... -1 80 v 100ms, non-operating .......................................................................................................... ............................................................................................. 100 v vaux ???????????????????????????............................................................................................... ........................................... -0.5 10.5 v +/- 100 ma sgnd ???????????????????????????............................................................................................... ........................................... +/- 100 ma ifb ???????????????????????????................................................................................................ .......................................... -0.5 5.7 v ref / ref_en ???????????????????????????.................................................................................................... ...................................... -0.3 3.6 v remote sense operation ........................................................................................................ .......................................................................................... 10 ma adaptive loop operation ....................................................................................................... ............................................................................................ 3.4 ma trim ???????????????????????????............................................................................................... ............................................ -0.3 3.6 v al ???????????????????????????................................................................................................. .......................................... -0.3 3.6 v vt ???????????????????????????................................................................................................. .......................................... -0.3 4.8 v vc to ?out ???????????????????????????......................................................................................... .................................................. -0.5 18 v +/- 1.8 a +out to ?out ???????????????????????????....................................................................................... .................................................... -1 62 v output current ???????????????????????????..................................................................................... ...................................................... 7.3 a internal operating temperature tgrade????????????????????..................................................................................................... ................................................... -40 125 oc m grade ???????????????????.................................................................................................... ................................................... -55 125 oc storage temperature t grade ???????????????????.................................................................................................... .................................................... -40 125 oc m grade ???????????????????.................................................................................................... .................................................... -65 125 oc
- 6 - prm48bh480 x 250a00 rev. 1.0 11/2012 electrical specifications electrical characteristics specifications apply over all line and load conditions, and trim from 20 v to 55 v, unless otherwise noted; boldface specifications apply over the temperature range of -40oc < t int < 125oc; all other specifications are at t int = 25oc unless otherwise noted. attribute symbol conditions / notes min typ max unit power input specification input voltage range v in continuous, operating 38 48 55 v v in slew rate dv in /dt 0 v in ? 55v 0.001 1000 v/ms initialization voltage v init internal micro controller initialization voltage 10 v initialization delay t init from v in first crossing v init 5.0 7.0 9.0 ms no load power dissipation p nl enable high, v in = 48 v 2.4 3.5 w input quiescent current i qc enable low, v in = 48v 14.5 20 ma input current i in_dc i out = 5.21a, v in =48 v, v out = 48 v 5.4 5.6 a input capacitance (internal) c in_int effective value, v in = 48 v (see fig. 13) 2 ? f ? input capacitance (internal) esr r cin effective value, v in =48 v 3 m ? power output specification output current i out standalone and master operation, see figure 1, soa 5.21 a output power p out standalone and master operation, see figure 1, soa 250 w switching frequency f sw v in = 48v v out = 48v, i out = 2.61a, t int = 25c 0.935 1.03 1.065 mhz over line, load, trim and temperature, exclusive of burst mode 0.70 1.065 mhz turn-on delay t on from v in first crossing v in_uvlo+_supv to enable high; t init expired 20 s ? from enable released to enable high, v in applied, t off, and t init expired startup sequence timeout t startup_seq from enable high to startup sequence complete 17 ms efficiency ambient amb v in = 48v, v out = 48v, i out = 5.21a, t int = 25c 95.7 96.7 % v in = 48v, v out = 48v, i out = 2.61a, t int = 25c 94.7 95.7 % v in = 38v to 55v , v out = 48v, i out = 5.21a, t int = 25c 95.0 % v in = 38v to 55v , i out = 5.21a, t int = 25c, over trim 92.0 % efficiency hot hot v in = 48v, v out = 48v, i out = 5.21a, t int = 100c 95.5 96.5 % v in = 48v, v out = 48v, i out = 2.61a, t int = 100c 94.5 95.8 % v in = 38v to 55v , v out = 48v, i out = 5.21a, t int = 100c 95.0 % v in = 38v to 55v , i out = 5.21a, t int = 100c, over trim 91.5 % efficiency over temperature >50% load and v out =48 v; over temperature 94.5 % >50% load; over temperature and trim 89.0 % output discharge current i od average value 0.5 ma output voltage ripple v out_pp v in =48 v, v out = 48 v, i out =5.21a, c out_ext = 0 f, 20 mhz bw 1000 1500 mv output inductance (parasitic) l out_par frequency @ 1.00 mhz, simulated j-lead model 2.5 nh output capacitance (internal) c out_int effective value, v out = 48 v (see fig. 13) 2 ? f ? output capacitance (internal) esr r cout effective value, v out = 48 v 3 m ?
- 7 - prm48bh480 x 250a00 rev. 1.0 11/2012 electrical characteristics specifications apply over all line and load conditions, and trim from 20 v to 55 v, unless otherwise noted; boldface specifications apply over the temperature range of -40oc < t int < 125oc; all other specifications are at t int = 25oc unless otherwise noted. power output specifications: adaptive loop operation output voltage setpoint v out_set no load, trim inactive, adaptive loop load line inactive 47.04 48 48.96 v output voltage trim range v out 20 55 v output voltage rise time t rise_vout from soft start initiated to output voltage settled 1.7 1.8 1.90 ms output voltage load regulation v out_reg_load adaptive loop load line inactive 0.02 0.2 % output voltage line regulation v out_reg_line adaptive loop load line inactive 0.02 0.2 % total regulation error v out_reg_total prm output voltage, adaptive loop load line inactive 0.2 % total al regulation error v out_reg_al vtm output voltage, total adaptive loop regulation, v out = 48 v, trim inactive 1 3 % vtm output voltage, total adaptive loop regulation, trim active, exclusive of external resistor tolerances 5 % output current limit i limit v in = 48v, v out = 48v, t int = 25c, constant current limit after supervisory limit detection time t lim_supv 5.7 6.5 7.3 a over line, load, trim and temperature 5.2 7.3 a load capacitance (electrolytic) c load_alel 0.1 ? esr 1.0 ? , see figure 31, total capacitance (c load_alel + c load_cer ) 47uf 47 ? f ? load capacitance (ceramic) c load_cer 2m ?? esr 200m ? , see figure 31 25 ? f ? load transient voltage deviation v trans 10% ? 100% load step, 10 a/ sec, 0 uf cout, deviation from initial setpoint 4.8 v load transient recovery time t trans 10% to100% load step, 10 a/sec, 0 uf cout, recovery to 90% of final value, adaptive loop load line inactive 100 ? s ? 10% to 100% load step, 10 a/sec, 0 uf cout, recovery to 90% of final value, adaptive loop load line active, val=1.25v 500 ? s ? power output specifications: slave operation rated current within an array i out_array slave operation within an array, up to 5 c case temperature differential, master-slave configuration 4.16 a slave operation within an array, up to 30 c case temperature differential, master-slave configuration 3.6 a rated power within an array p out_array slave operation within an array, up to 5 c case temperature differential, master-slave configuration 200 w slave operation within an array, up to 30 c case temperature differential, master-slave configuration 175 w current sharing difference (master to slave) i out_share_ms equal input, and output voltage at full load; v in = 48 v, v out = 48 v 15 % equal input and output voltage at full load; over line and trim, with 25c t c 100c 5c part-part temp mismatch 15 % equal input, and output voltage at full load; over line and trim, with 25c t c 100c and 30c part-part temp. mismatch 20 % current sharing difference (slave to slave) i out_share_ss equal input, output, and share voltage at full load; v in = 48 v, v out = 48 v 5 % equal input, output and share voltage at full load; over line and trim, with 25c t c 100c and 5c part-part temp mismatch 10 % equal input, output, and share voltage at full load; over line and trim, with25c t c 100c and 30c part-part temp mismatch 15 % maximum array size n prms_parallel maximum number of parallel devices, master-slave configuration 5 prms power output specifications: remote sense operation output voltage range v out 20 55 v rated current within an array i out_array remote sense operation within an array, up to 5c case temperature differential 4.7 a remote sense operation within an array, up to 30c case temperature differential 3.6 a rated power within an array p out_array remote sense operation within an array, up to 5c case temperature differential 225 w remote sense operation within an array, up to 30c case temperature differential 175 w current sharing difference i out_share_rs equal input, output, and control node voltage at full load; v in = 48 v, v out = 48 v 5 % equal input, output and control node voltage at full load; over line and trim, with 25c t c 100c and 5c part-part temp mismatch 10 % equal input, output, and control node voltage at full load; over line and trim, with 25c t c 100c and 30c part-part temp. mismatch (worst case) 15 % maximum array size n prms_parallel maximum number of parallel devices, remote sense configuration, control node externally driven 10 prms
- 8 - prm48bh480 x 250a00 rev. 1.0 11/2012 electrical characteristics specifications apply over all line and load conditions, and trim from 20 v to 55 v, unless otherwise noted; boldface specifications apply over the temperature range of -40oc < t int < 125oc; all other specifications are at t int = 25oc unless otherwise noted. powertrain protections input undervoltage turn-on v in_uvlo+ 24.5 26.0 v input undervoltage turn-off v in_uvlo- instantaneous powertrain shutdown, detected after t blnk 22.0 22.7 v input undervoltage hysteresis v uvlo_hyst (v in_uvlo+ ) - (v in_uvlo- ) 1.8 2.2 2.5 v input overvoltage turn-on v in_ovlo+ 56.0 62.6 v input overvoltage turn-off v in_ovlo- instantaneous powertrain shutdown, detected after t blnk 63.6 67.3 v input overvoltage hysteresis v ovlo_hyst (v in_ovlo+ ) - (v in_ovlo- ) 0.7 1.0 1.4 v output overvoltage threshold v out_ovp+ instantaneous powertrain shutdown, detected after t blnk 56.0 57.9 60.0 v minimum current limited vout v out_uvp 12 v overtemperature shutdown setpoint t int_otp instantaneous powertrain shutdown, detected after t blnk 125 oc output power limit p prot 250 w short circuit vout threshold v sc_vout 8.8 v short circuit vout recovery threshold v sc_voutr 9.5 v short circuit control node threshold v sc_vcn 7.2 v short circuit control node recovery threshold v sc_vcn 6.9 v short circuit timeout t sc short circuit fault detected after v sc_vout and v sc_vcn thresholds persist for this time 5 ms short circuit recovery time t scr excludes t off 75 ms overcurrent (ifb ), and input over/undervoltage blanking time t blnk 50 120 150 ? s ? overtemperature, output overvoltage and enable shutdown response time (hardware) t prot 2 ? s ? powertrain supervisory limits input undervoltage turn-on (supervisory) v in_uvlo+_supv powertrain shutdown, after supervisory detection t lim_supv 35.8 37.0 v input undervoltage turn-off (supervisory) v in_uvlo-_supv powertrain shutdown, after supervisory detection t lim_supv 32.2 33.6 v input undervoltage hysteresis (supervisory) v uvlo_hyst_supv (v in_uvlo+_supv ) - (v in_uvlo-_svpv ) 1.9 2.2 2.5 v input overvoltage turn-on (supervisory) v in_ovlo+_supv powertrain shutdown after supervisory detection t lim_supv 56.0 57.7 v input overvoltage turn-off (supervisory) v in_ovlo-_supv powertrain shutdown after supervisory detection t lim_supv 58.9 60.0 v input overvoltage hysteresis (supervisory) v ovlo_hyst_supv (v in_ovlo+_supv ) - (v in_ovlo-_supv ) 0.8 1.2 1.7 v undertemperature shutdown setpoint (supervisory) t int_utp t grade -40 oc m grade -55 oc supervisory limit response time t lim_supv 150 ? s ?
- 9 - prm48bh480 x 250a00 rev. 1.0 11/2012 signal specifications specifications apply over all line and load conditions, t int = 25 oc and output voltage from 20 v to 55v, unless otherwise noted. boldface specifications apply over the temperature range of -40 oc < t int < 125 oc (t-grade). enable ? the enable pin enables and disables the prm ? in prm array configurations, enable pins should be connected in order to synchronize startup ? enable is 5.0v with 1.8ma source capability during normal operation signal type state attribute symbol conditions / notes min typ max unit analog output regular operation enable voltage v enable 4.7 5.0 5.3 v enable available current i enable_op 1.8 ma startup enable source current i enable_en after t off 90 ? a ? minimum time to start t off 13.5 15 16.5 ms digital input / output startup enable enable threshold v enable_en 2.5 3.2 v standby enable disable threshold v enable_dis 0.97 2.4 v enable resistance (external) r enable_ext resistance to sgnd required to disable the prm 235 ? digital output fault enable sink current to sgnd i enable_fault enable voltage 1 v or above 4 ma vaux: auxilary voltage source ? intended to power auxiliary circuits ? 9.0v during normal operation with 5ma source capability signal type state attribute symbol conditions / notes min typ max unit analog output regular operation vaux voltage v vaux 8.6 9.0 9.5 v vaux available current i vaux 5 ma vaux voltage ripple v vaux_pp iout = 0a, c vaux_ext = 0. maximum specification includes powertrain operation in burst mode. 100 400 mv transition vaux capacitance (external) c vaux_ext 0.04 ? f ? vaux fault response time t fr_vaux from fault recognition to vaux = 1.5 v 30 ? s ? vc: vtm control ? pulsed voltage source used to power and synchronize downstream vtm during startup ? 14 v, 10 ms typical voltage pulse signal type state attribute symbol conditions / notes min typ max unit analog output startup vc voltage v vc_start connected to vtm vc or equivalent, i vc = 115ma, c vc = 3.2uf 13 14 18 v vc available current i vc_start v c =14 v, v in > 20 v 200 ma vc duration t vc 7 10 16 ms vc slew rate dvc/dt connected to vtm or equivalent, i vc = 115ma, c vc = 3.2uf 0.02 0.25 v/ ? s enable to vc delay t enable-vc 20 ? s ?
- 10 - prm48bh480 x 250a00 rev. 1.0 11/2012 sgnd: signal ground ? all control signals must be referenced to this pin, with the exception of vc ? sgnd is internally connected to ?in and ?out signal type state attribute symbol conditions / notes min typ max unit analog input / output any maximum allowable current i sgnd -100 100 ma trim ? trim is used to select operating mode and trim the output voltage in adaptive loop operation ? internal pullup to v cc_int through10k ? resistor ? when pulled below 0.45v during power up, remote sense / slave operation is selected ? when allowed to pull up above 0.55 during power up, adaptive loop operation is selected ? operating mode is latched during power up and cannot be changed unless input power is cycled signal type state attribute symbol conditions / notes min typ max unit analog input normal operation internally generated vcc v cc_int 3.20 3.28 3.36 v internal pullup resistance to v cc_int r trim_int 0.5% tolerance resistor 9.83 10 10.18 k ? mode detect mode detection delay t mode_detect from enable high to mode detected, after v in first applied 100 140 200 s ? remote sense enable threshold v rs_mode_en pull below this value during application of power to enable remote sense / slave operation 0.45 v remote sense disable threshold v rs_mode_dis pull above this value during application of power to enable adaptive loop operation 0.55 v trim (adaptive loop operation only) ? provides dynamic trim control over the prm output voltage in adaptive loop operation ? sampled prior to every startup to detect if trim is active or inactive ? output voltage is equal to 20 times the voltage at the trim pin when applied trim voltage is within the active range ? trim state is latched during normal operation and cannot be changed until startup is initiated signal type state attribute symbol conditions / notes min typ max unit analog input startup trim enable threshold v trim_en pull below this value during startup to enable trim control 3.10 v trim disable threshold v trim_dis pull above this value during startup to disable trim control 3.20 v minimum trim disable resistance r trim_dis_min minimum trim resistance required to disable trim 10 m ? trim capacitance (external) c trim_ext 100 pf ? trim sample delay t enable_trim from enable high to trim sampled 100 140 200 s ? normal operation trim pin analog range v trim_range see figure 26 1.00 2.75 trim gain g trim v out / v trim, v trim applied within active range 20 v/v trim accuracy % acc_trim vout accuracy, exclusive of external resistor tolerance 0.5 2 % v out referred trim resolution v out_res 200 mv trim latency t trim_lat 60 120 240 ? s ? trim bandwidth bw trim -3db point 1.2 khz
- 11 - prm48bh480 x 250a00 rev. 1.0 11/2012 al: adaptive loop (adaptive loop operation only) ? provides adaptive loop load line programming in adaptive loop operation ? internal pullup to v cc_int through10k ? resistor ? sampled prior to every startup to detect if adaptive loop load line is active or inactive ? leave open to disable adaptive loop load line ? not used in remote sense operation signal type state attribute symbol conditions / notes min typ max unit analog input startup al enable threshold v al_en pull below this value during startup to enable al load line 3.10 v al disable threshold v al_dis pull above this value to disable al load line 3.20 v minimum al disable resistance r al_dis_min minimum al resistance required to disable al load line 10 m ? al capacitance (external) c al_ext 100 pf ? al sample delay t enable_al from enable high to al sampled 100 140 200 s ? normal operation internally generated vcc v cc_int 3.20 3.28 3.36 v internal pullup resistance to v cc_int r al_int 0.5 % tolerance resistor 9.83 10 10.18 k ? al pin analog range v al_range 0 3.10 v al gain g al positive correction slope, vt inactive 1.0 ? /v al load line accuracy % acc_ll_al full load slope accuracy exclusive of external resistor tolerance 0.5 2 % al load line resolution ll al_res 3 m ? maximum output referred compensation v out_al_max maximum increase from no load setpoint, v out ? 55 v 5 v al latency t al_lat 60 120 240 ? s ? al bandwidth bw al -3db point 1.2 khz vt: vtm temperature (adaptive loop operation only) ? vtm temperature compensation for adaptive loop regulation ? adjusts the slope of the adaptive loop load line to account for changes in vtm output resistance over temperature ? connect to tm pin of compatible downstream vtm to enable temperature compensation ? leave disconnected to disable temperature compensation signal type state attribute symbol conditions / notes min typ max unit analog input normal operation internal resistance to sgnd r vt_int 80 k ? vt enable threshold v vt_en 2.1 v vt disable threshold v vt_dis pull below this value to disable vt temperature compensation 1.9 v vt disable default temperature t vt_dis default al temperature setting when vt disabled 25 c vt analog range v vt_op 2.18 3.98 v vt temperature coefficient tc vt vt within active range, referenced to 2.98v 30 %/v tc vt vtm tm voltage applied, .01v/ k, referenced to 25c 0.3 %/c vt resolution tc vt_res vtm tm voltage applied, .01v/ k 0.4 c vt latency t vt_lat 60 120 240 ? s ? bandwidth bw vt -3db point 1.5 khz
- 12 - prm48bh480 x 250a00 rev. 1.0 11/2012 ref / ref_en ref: reference (adaptive loop operation only) ? functions as ref pin in adaptive loop operation ? ref represents the internal voltage reference for the voltage control circuit ? v out approximately equal to 20 times ref voltage signal type state attribute symbol conditions / notes min typ max unit analog output regular operation ref voltage v ref v out = 48v, trim inactive 2.4 v ref to v out scale factor g ref_vout v out / v ref 20 v/v ref resistance (external) r ref_ext 10 m ? ref capacitance (external) c ref_ext 200 pf ? ref voltage ripple v ref_pp includes burst mode, 20mhz bw 25 mv transition enable to ref delay t enable_ref enable low to ref low 120 ? s ? vaux to ref delay t vaux_ref vaux = 8.1 v to ref soft start ramp initiated 1 ms ref_en: reference enable (remote sense and slave operation only) ? functions as ref_en pin in remote sense and slave operation ? ref_en signals successful startup and powertrain ready to operate ? intended to power and enable the external feedback circuit reference in remote sense operation ? 3.25v, 4ma regulated voltage source signal type state attribute symbol conditions / notes min typ max unit analog output regular operation ref_en voltage v ref_en ref_en unloaded 2.72 3.25 3.37 v ref_en source impedance r out_ref_en 50 100 ? ref_en available current i ref_en 4 ma ref_en capacitance (external) c ref_en_ext includes burst mode, 20mhz bw 0.1 ? f ? ref_en voltage ripple v ref_en_pp includes burst mode 25 mv transition enable to ref_en delay t enable_ref_en enable low to ref_en low 1 ms vaux to ref_en delay t vaux_ref_en vaux = 8.1 v to ref_en high 1 ms
- 13 - prm48bh480 x 250a00 rev. 1.0 11/2012 share / control node share (adaptive loop and slave operation only) ? functions as share pin in master slave array configuration ? current share bus for array operation (master/slave scheme) ? sources current and provides share signal in master operation ? sinks constant current when externally driven in active range (slave operation) signal type state attribute symbol conditions / notes min typ max unit analog output standalone / master operation share voltage active range v share 0.79 7.40 v share available current i share v share > 0.79v 2.5 ma share resistance to sgnd r share 93.3 k ? analog input slave operation share sink current i share_sink v share > 0.79v 0.25 0.50 0.75 ma ? control node (remote sense operation only) ? functions as control node pin in remote sense operation ? modulator control node voltage sets power train timing ? driven by external error amplifier in remote sense operation ? sinks constant current when externally driven in active range ? sources current, and clamps voltage to 0.79v when pulled below active range signal type state attribute symbol conditions / notes min typ max unit analog input regular operation control node voltage active range v cn 0.79 7.40 v control node source current i cn_low v cn < 0.79v 2.5 ma control node sink current i cn_sink v cn > 0.79v 0.25 0.50 0.75 ma control node resistance to sgnd r cn 93.3 k ? ifb: current feedback (remote sense operation only) ? functions as ifb pin in remote sense operation ? a voltage proportional to the prm output current must be supplied externally to the ifb pin in order for the device to proper ly protect overcurrent events and to enable output current limit (clamp) ? overcurrent protection trip will cause instantaneous powertrain shutdown, detected after t blnk ?not used for adaptive loop operation signal type state attribute symbol conditions / notes min typ max unit analog input regular operation current limit (clamp) threshold v ifb_il v in = 48v v; v out = 48v t int = 25 c 1.90 2.00 2.10 v over line, trim, and temperature 1.85 2.15 v overcurrent protection threshold v ifb_oc not production tested; guaranteed by design; t int = 25 c 2.58 2.69 2.80 v not production tested; guaranteed by design; over line, trim, and temperature 2.09 2.17 v ifb input impedance r ifb 2.09 2.13 2.17 k ? current limit bandwidth bw il 2.0 khz nc: no connect ? reserved for factory use only ? no connections should be made to these pins
- 14 - prm48bh480 x 250a00 rev. 1.0 11/2012 functional block diagram +out -out l q1 q2 q3 cout +in -in cin q4 share/ control node 57.6k 35.7k 1000pf enable modulator enable trim 3.3v 10k 1000pf 10k nc nc 10k 10k 0.01uf al 20k 60.4k vt 2200pf vaux 0.01uf 2.1k 30.1 ifb 0.01uf ref/ ref_en 10 k 6800 pf control and monitoring otp undervoltage lockout output short circuit overvoltage lockout output overvoltage protection current limit voltage reference 0.5ma 2.5ma min adaptive loop in out pgnd sgnd 1.58k 30.1k 3.3v linear regulator vcc sgnd internal vcc regulator vc error amplifer pgnd sgnd
- 15 - prm48bh480 x 250a00 rev. 1.0 11/2012 high level functional state diagram conditions that cause state transitions are shown along arro ws. sub-sequence activities listed inside the state bubbles. startup sequence t on expired enable: 1.8ma to high vc pulse ref_en active adaptive loop and trim modes latched rs mode latched at first enable after vin applied only powertrain active standby sequence enable: 10ua to low t off expired enable: 90ua to high powertrain stopped application of vin enable rising edge enable falling edge, output ovp or otp detected fault sequence enable pulsed: 25ma to low powertrain stopped v in > uvlo+ enable falling edge, output ovp, or otp detected t startup_seq expired sustained operation enable: 1.8ma to high powertrain active input ovlo or uvlo, output uvp, or utp detected short circuit detected input ovlo or uvlo, output uvp, or utp detected fault auto- recovery
- 16 - prm48bh480 x 250a00 rev. 1.0 11/2012 timing diagrams (adapt ive loop operation page 1) module inputs are shown in blue; module outputs are shown in brown. ref v out enable share +in vc vaux trim iout v vc_start 3.3v 2.4v t vc t blnk 1 input ? power ? on ? and ? uv ? turn \ on 3 al active 4 input ? ov 5 input ? ov ? recovery 6 enable ? disable 7 enable ? release 8 full ? load ? applied 9 output ? ov t off t on t on t blnk t blnk t aux_ref t prot t prot bidir bidir bidir output output output output input input al v init t off 1v 48v 55v 2.75v 1.0v 20v 0v 2 trim inactive al ? = ? 1v t enable_vc v in_ovlo v in_uvlo v share_max v share_min i limit v enable v enable_en v out_ovp+ v out_max v out_nom v out_min v aux t startup_seq al ? = ? 1v input v ref firstenb: ? tr ? not ? low ? = ? not ? rs ? mode ? tr ? high ? = ? trim ? inactive ? for ? this ? enabled ? period al ? not ? high ? = ? al ? active ? for ? this ? enabled ? period tr ? high ? = ? trim ? inactive ? for ? this ? enabled ? period al ? not ? high ? = ? al ? active ? for ? this ? enabled ? period tr ? high ? = ? trim ? inactive ? for ? this ? enabled ? period al ? not ? high ? = ? al ? active ? for ? this ? enabled ? period soft start trim ignored vout ? increases ? by ? v al * ? g al * ? i out trim ? and ? al ? pins ? sampled ? soft start micro \ controller ? initialized current ? sense ? activated, ? and ? output ? increase ? due ? to ? al ? after ? t startup_seq ? expires
- 17 - prm48bh480 x 250a00 rev. 1.0 11/2012 timing diagrams (adapti ve loop operation page 2) ref v out enable share +in vc vaux trim iout v in_ovlo v enable_en v enable v vc_start v aux v share_min i limit v share_max 10 input ? power ? on ? and ? uv ? turn \ on ? 12 output ? short ? circuit 15 output ? power ? limit ? protection 16 current ? limit ? event 17 input ? power ? off ? and ? uv ? turn \ off t off t sc t blnk 20v input bidir bidir bidir output output output output input input 2.75v al v init 1 v 3.3v 55v 2.4v 48v 1 v 2.4v 2.75v 3.3v 1v 14 ot ? shutdown ? and ? recovery 13 enable toggling 11 al ? inactive ? and ? trim ? active v out_max v out_min v out_nom v in_uvlo t startup_seq firstenb: ? tr ? not ? low ? = ? not ? rs ? mode ? tr ? not ? high ? = ? trim ? active ? for ? this ? enabled ? period al ? high ? = ? al ? inactive ? for ? this ? enabled ? period tr ? not ? high ? = ? trim ? active ? for ? this ? enabled ? period al ? high ? = ? al ? inactive ? for ? this ? enabled ? period tr ? high ? = ? trim ? inactive ? for ? this ? enabled ? period al ? not ? high ? = ? al ? active ? for ? this ? enabled ? period tr ? high ? = ? trim ? inactive ? for ? this ? enabled ? period al ? not ? high ? = ? al ? active ? for ? this ? enabled ? period t lim_supv t scr +t off t blnk al ? pin ? ignored v out = ? v trim * ? 20 v out clamped ? to ? 55v ? for ? v trim > ? 2.75v al ? active vout ? increase ? due ? to ? iout ? and ? al ? after ? t startup_seq ? expires operating ? mode trim ? and ? al ? state ? detected ? micro \ controller ? initialized
- 18 - prm48bh480 x 250a00 rev. 1.0 11/2012 timing diagrams (remote sense operation page 1) ref_en v out enable control ? node +in vc vaux trim ifb v enable_en v enable v vc_start v cn_max v aux v ref_en t vc v ifb_oc t blnk 1 input ? power ? on ? and ? uv ? turn \ on t < t blnk 2 quick ? oc ? (t - 19 - prm48bh480 x 250a00 rev. 1.0 11/2012 timing diagrams (remote sense operation page 2) ref_en v out enable control ? node +in vc vaux trim ifb 9 start ? up ? with minimum ? < ? dv in /dt < ? 1.2v/ms 10 output ? short ? circuit 11 output ? power ? limit ? protection 12 current ? limit ? event 13 input ? uv t off t sc - 20 - prm48bh480 x 250a00 rev. 1.0 11/2012 typical performance characteristics the following figures present typical performance at t c = 25oc, unless ot herwise noted. figure 1 dc safe operating area (soa) figure 2: no load power dissipation vs. v in , module enabled figure 3: no load power dissipation vs. v in , module disabled figure 4: total efficiency and power dissipation vs. v in and i out v out = 20 v, t case = -40 c figure 5: total efficiency and power dissipation vs. v in and i out v out = 20 v, t case = 25 c figure 6: total efficiency and power dissipation vs. v in and i out v out = 20 v, t case = 100 c 0 50 100 150 200 250 300 0.0 1.0 2.0 3.0 4.0 5.0 6.0 20 25 30 35 40 45 50 55 60 output power [w] output current [a] output voltage [v] dc safe operating area current power current power 1 1.5 2 2.5 3 3.5 4 38 40 42 44 46 48 50 52 54 56 power dissipation [w] input voltage [v] no load power dissipation vs. line module enabled - 48 vout tcase: ?\ 40c tcase: ? 25c tcase: ? 100c 0.4 0.5 0.6 0.7 0.8 0.9 1 38 40 42 44 46 48 50 52 54 56 power dissipation [w] input voltage [v] no load power dissipation vs. line module disabled - enable = low tcase: ?\ 40c tcase: ? 25c tcase: ? 100c 0 2 4 6 8 10 12 70 75 80 85 90 95 100 0 0.75 1.5 2.25 3 3.75 4.5 5.25 power dissipation [w] efficiency [%] load current [a] efficiency & power dissipation vout = 20 v tcase =-40 c vin: ? 38 ? v vin: ? 48 ? v vin: ? 55 ? v 0 2 4 6 8 10 12 70 75 80 85 90 95 100 0 0.75 1.5 2.25 3 3.75 4.5 5.25 power dissipation [w] efficiency [%] load current [a] efficiency & power dissipation vout = 20 v tcase =25 c vin: ? 38 ? v vin: ? 48 ? v vin: ? 55 ? v 0 2 4 6 8 10 12 14 65 70 75 80 85 90 95 100 0 0.75 1.5 2.25 3 3.75 4.5 5.25 power dissipation [w] efficiency [%] load current [a] efficiency & power dissipation vout = 20 v tcase =100 c vin: ? 38 ? v vin: ? 48 ? v vin: ? 55 ? v
- 21 - prm48bh480 x 250a00 rev. 1.0 11/2012 figure 7: total efficiency and power dissipation vs. v in and i out v out = 48 v, t case = -40 c figure 8: total efficiency and power dissipation vs. v in and i out v out = 48 v, t case = 25 c figure 9: total efficiency and power dissipation vs. v in and i out v out = 48 v, t case = 100 c figure 10: total efficiency and power dissipation vs. v in and i out v out = 55 v, t case =-40 c figure 11: total efficiency and power dissipation vs. v in and i out v out = 55 v, t case = 25 c figure 12: total efficiency and power dissipation vs. v in and i out v out = 55 v, t case =100 c 0 2 4 6 8 10 12 14 84 86 88 90 92 94 96 98 0 0.75 1.5 2.25 3 3.75 4.5 5.25 power dissipation [w] efficiency [%] load current [a] efficiency & power dissipation vout = 48 v tcase =-40 c vin: ? 38 ? v vin: ? 48 ? v vin: ? 55 ? v 0 2 4 6 8 10 12 14 84 86 88 90 92 94 96 98 0 0.75 1.5 2.25 3 3.75 4.5 5.25 power dissipation [w] efficiency [%] load current [a] efficiency & power dissipation vout = 48 v tcase =25 c vin: ? 38 ? v vin: ? 48 ? v vin: ? 55 ? v 0 2 4 6 8 10 12 14 84 86 88 90 92 94 96 98 0 0.75 1.5 2.25 3 3.75 4.5 5.25 power dissipation [w] efficiency [%] load current [a] efficiency & power dissipation vout = 48 v tcase =100 c vin: ? 38 ? v vin: ? 48 ? v vin: ? 55 ? v 0 2 4 6 8 10 12 14 16 18 20 78 80 82 84 86 88 90 92 94 96 98 0 0.75 1.5 2.25 3 3.75 4.5 5.25 power dissipation [w] efficiency [%] load current [a] efficiency & power dissipation vout = 55 v tcase =-40 c vin: ? 38 ? v vin: ? 48 ? v vin: ? 55 ? v 0 2 4 6 8 10 12 14 16 18 20 78 80 82 84 86 88 90 92 94 96 98 0 0.75 1.5 2.25 3 3.75 4.5 5.25 power dissipation [w] efficiency [%] load current [a] efficiency & power dissipation vout = 55 v tcase =25 c vin: ? 38 ? v vin: ? 48 ? v vin: ? 55 ? v 0 2 4 6 8 10 12 14 16 18 20 78 80 82 84 86 88 90 92 94 96 98 0 0.75 1.5 2.25 3 3.75 4.5 5.25 power dissipation [w] efficiency [%] load current [a] efficiency & power dissipation vout = 55 v tcase =100 c vin: ? 38 ? v vin: ? 48 ? v vin: ? 55 ? v
- 22 - prm48bh480 x 250a00 rev. 1.0 11/2012 figure 13 effective internal input and output capacitance vs. voltage ? ceramic type figure 14: power train switching frequency and periodic input charge vs. v in , v out ; i out = 5.21 a figure 15: power train switching frequency and periodic output charge vs. v in , v out ; i out = 5.21 a figure 16 output power vs. share / control node voltage; v in = 48 v, v out = 48 v, t case = 25 c figure 17: typical share / control node voltage vs. t case and i out; v in = 48 v, v out =48 v 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 5 10 15 20 25 30 35 40 45 50 55 effective capacitance (f) applied voltage [v] effective internal input and output capacitance vs. applied voltage input ? and ? output ? capacitance ? (uf) input and output capacitance 0 2 4 6 8 10 12 14 16 850 875 900 925 950 975 1000 1025 1050 38 40 42 44 46 48 50 52 54 56 total input charge per switching cycle [c] f sw [khz] input voltage [v] power train switching frequency and periodic input charge vs. input voltage - full load vout: ? 20 ? v vout: ? 48 ? v vout: ? 55 ? v input charge (c) switching frequency (khz)) 0 2 4 6 8 10 12 14 16 850 875 900 925 950 975 1000 1025 1050 38 40 42 44 46 48 50 52 54 56 total output charge per switching cycle [c] f sw [khz] input voltage [v] power train switching frequency and periodic output charge vs. input voltage - full load vout: ? 20 ? v vout: ? 48 ? v vout: ? 55 ? v output charge (c) switching frequency (khz)) 0 50 100 150 200 250 2.533.544.555.566.57 output power [w] v control_node [v] output power vs. share / control node voltage vin = 48 v, vout = 48 v, tcase = 25 c typical 4.3 4.3 4.1 5.8 5.9 5.7 4 4.5 5 5.5 6 6.5 \ 40 \ 20 0 20406080100 v control node [v] case temperature [c] share / control node voltage vs. case temperature vin = 48 v vout = 48 v iout: ? 2.08 ? a iout: ? 5.21 ? a
- 23 - prm48bh480 x 250a00 rev. 1.0 11/2012 figure 18 powertrain characteristics vs. i out, v in resistive load, v out = 20v figure 19 powertrain characteristics vs. i out, v in resistive load, v out = 48v figure 20 powertrain characteristics vs. i out, v in resistive load, v out = 55v figure 21 magnitude of powertrain dynamic input impedance vs. i out , v in ; v out = 20 v figure 22 magnitude of powertrain dynamic input impedance vs. i out , v in ; v out = 48 v figure 23 magnitude of powertrain dynamic input impedance vs. i out , v in ; v out = 55 v 0 25 50 75 100 125 150 \ 5 \ 2.5 0 2.5 5 7.5 10 0 0.75 1.5 2.25 3 3.75 4.5 5.25 r eq [ ? ] g cn [db] load current[a] dc modulator gain and powertrain equivalent resistance vs. output current - vout = 20 v vin: ? 38 ? v vin: ? 48 ? v vin: ? 55 ? v r eq ( ? ) g cn (db) 0 50 100 150 200 250 300 \ 20 \ 15 \ 10 \ 5 0 5 10 0 0.75 1.5 2.25 3 3.75 4.5 5.25 r eq [ ? ] g cn [db] load current[a] dc modulator gain and powertrain equivalent resistance vs. output current - vout = 48 v vin: ? 38 ? v vin: ? 48 ? v vin: ? 55 ? v r eq ( ? ) g cn (db) 0 50 100 150 200 250 300 \ 20 \ 15 \ 10 \ 5 0 5 10 0 0.75 1.5 2.25 3 3.75 4.5 5.25 r eq [ ? ] g cn [db] load current[a] dc modulator gain and powertrain equivalent resistance vs. output current - vout = 55 v vin: ? 38 ? v vin: ? 48 ? v vin: ? 55 ? v r eq ( ? ) g cn (db) 0 20 40 60 80 100 120 0 0.75 1.5 2.25 3 3.75 4.5 5.25 r in [ ? ] load current[a] powertrain equivalent input resistance vs. output current - vout = 20 v vin: ? 38 ? v vin: ? 48 ? v vin: ? 55 ? v 0 10 20 30 40 50 0 0.75 1.5 2.25 3 3.75 4.5 5.25 r in [ ? ] load current[a] powertrain equivalent input resistance vs. output current - vout = 48 v vin: ? 38 ? v vin: ? 48 ? v vin: ? 55 ? v 0 10 20 30 40 50 0 0.75 1.5 2.25 3 3.75 4.5 5.25 r in [ ? ] load current[a] powertrain equivalent input resistance vs. output current - vout = 55 v vin: ? 38 ? v vin: ? 48 ? v vin: ? 55 ? v
- 24 - prm48bh480 x 250a00 rev. 1.0 11/2012 general characteristics specifications apply over all line and load conditions, t int = 25 oc and output voltage from 20 v to 55v, unless otherwise noted. boldface specifications apply over the temperature range of -40 oc < t int < 125 oc (t-grade). attribute symbol conditions / notes min typ max unit mechanical length l 21.8 22.0 22.3 mm (.86) (0.87) (.88) in width w 16.3 16.5 16.8 mm (0.64) (0.65) (0.66) in height h 6.48 6.73 6.98 mm (0.255) (0.265) (0.275) in volume vol no heat sink 2.44 cm3 (0.15) in3 weight w 7 g lead finish nickel 0.51 2.03 ? m ? palladium 0.02 0.15 gold 0.003 0.050 thermal operating internal temperature t int t grade -40 125 oc m grade -55 125 oc thermal impedance int-case 2 oc/w int-lead 9 oc/w thermal capacity 5 ws/oc assembly peak compressive force applied to case (z-axis) supported by j-lead only 3 lbs 5.33 lbs / in 2 storage temperature t st t grade -40 125 oc m grade -65 125 oc moisture sensitivity level msl msl 6, 245c reflow msl5, 225c reflow esd rating human body model, "jedec jesd 22-a114c.01" 1000 v charged device model, "jedec jesd 22-c101d" 400 soldering peak temperature during reflow under msl 6 conditions above 245 oc under msl 5 conditions above 225 oc maximum time above 217 oc 150 s peak heating rate during reflow 1.5 2 oc / s peak cooling rate post reflow 2.5 3 oc / s reliability and agency approvals mtbf telcordia issue 2 - method i case 1; ground benign, controlled 5.28 mhrs mil-hdbk-217plus parts count - 25c ground benign, stationary, indoors / computer profile 5.28 mhrs agency approvals / standards c tuv us en60950-1, ul/csa 60950-1 ce mark low voltage directive (2006/95/ec) rohs 6 of 6
- 25 - prm48bh480 x 250a00 rev. 1.0 11/2012 pin functions +in, -in input power pins +out, -out output power pins. module cannot sink current. enable this pin turns the supply on and off. the pin is both an input and an output and can provide the following features: ? delayed start: upon application of voltage (>uvlo) to the module power input and after t off , the enable pin will source a constant 90 a current. ? output enable: when enable is allowed to pull up above the enable threshold, the enable pin will pull up to 5.0v with 1.8ma source capabi lity, and the module will be enabled. ? output disable: enable may be pulled down externally in order to disable the module. pull down resistance should be less than 235 ? to sgnd. ? fault detection flag: the enable 5.0v voltage source is internally turned off when a f ault condition is latched. enable control should be implemented using an open collector configuration. it is not recommended to drive this pin externally. vaux: auxiliary voltage source use this pin to power external devices with a non-isolated 9.0 v supply, with up to 5 ma load capability, switched with enable input. do not place a capacitor over 0.04 f on this pin. sgnd: signal ground this is a low current pin which pr ovides a kelvin connection to the prm?s internal signal ground. use this pin as the ground reference for external circuitry and signals to avoid voltage drops caused by high currents on power returns. in array configurations, sgnd pins should be star connected at a single point. a series resistor (~1 ? ) to the star location is recommended to decouple return currents. vc: vtm control this output pin is used to temporarily provide v cc voltage to connected vtms during start up. the pulse is nominally 14v, 10 ms wide. a vtm can self-power once its input voltage reaches 26v. the prm output must be checked to make sure it reaches this threshold voltage before the vc pulse expires. t rim the trim pin is used to select the operating mode and to trim the prm output when adaptive loop operating mode is selected. the trim pin has an internal pull-up to v cc_int through a 10 k ? resistor. operating mode select: if trim is pulled below 0.45 v during the first startup after v in is applied, remote sense / slave operation is selected. otherwise, adaptive loop operation is selected. this selection persists until v in is removed from the part, and is not changed by fault or disable events. \ output voltage trim: sets the output voltage of the prm in adaptive loop operation. if trim is permitted to pull up to 3.20 v or higher during start up, trim is disabled, and the output is set to the nominal of 48v. if trim is held between 1.00 v to 2.75 v during start up, trim is enabled, and the output is scal ed by a factor of 20 resulting in an output voltage range of 20 v to 55 v. this selection persists until the prm is restarted with the enable pin, or due to fault auto-recovery. al: adaptive loop (adaptive loop operation) this input pin allows you to set the adaptive loop load line. every volt on this pin represents 1.0 ? of positive output slope. there is an internal 10 k ? pullup resistor to v cc_int . if al is permitted to pull up to 3.20 v or higher during start up, the adaptive loop load line is disabled. this selection persists until the prm is restarted with the enable pin, or due to fault auto-recovery. vt: vtm temperature (adaptive loop operation) this pin is used in the adaptive loop compensation algorithm to account for the vtm output resistance variation as a function of temperature. the vtm tm pin provides this voltage, scaled as the temperature in k (kelvin) divided by 100, so 25 c is 2.98 v. leave disconnected or pull below 1.9v to disable. the adjustment is fixed at 0.3 %/c relative to the value at 25 c
- 26 - prm48bh480 x 250a00 rev. 1.0 11/2012 ref: reference (adaptive loop operation) this output pin allows you to monitor the internal reference voltage in adaptive loop operation. during normal operation it represents the output voltage sc aled by a factor of 20. in adaptive loop operation this pin is for monitoring purposes only and should not be driven or loaded externally. ref_en: reference enable (remote sense operation) in remote sense operation this pin outputs a regulated 3.25v, 4ma voltage source. it is enabled only after successful start up of the prm powertrain ref_en is intended to power the output current transducer and also the voltage reference for the external control loop. powering the reference generator with ref_en helps provide a controlled start up, since the output voltage of the system is able to track the reference level as it comes up. share (adaptive loop and slave operation) this bus sets the output current level for all the prm modules when operating in an array (master-slave configuration). connect them together among the modules in the shared bus. one prm should be configured as a master by connecting trim for adaptive loop operation. all other prms should be configured as slaves by pulling t heir respective trim pins low. this pin can be used to monitor the error voltage externally. 0 to 100% load is represented by a voltage between 0.79 v and 7.40. control node (remote sense operation) in remote sense operation, this is the input to the modulator which determines the powertrain timing and ultimately the module output power. an internal 0.5 ma current sink is always active. the bi-directional buffer between control node and the modulator has two states. in normal operation, control node will be abov e the 0.79 v switching threshold, and will drive the modu lator through the buffer. an internal 7.4v clamp determines the maximum output power that can be requested of the modulator. when control node falls below 0.79 v, the converter will stop switching. an internal circuit clamps the modulator input to 0.79 v, and a buffer will source up to 2.5 ma out of the pin at that clamp level. for this reason, the output impedance of the amplifier driving control node must be taken into account. a rail-to-rail operational amplifier with low output impedance is always recommended. the powertrain small signal (plant) response consists of a single pole determined by the load resistance, the powertrain equivalent output resistance, and the total output capacitance (internal and external to the module). both the modulator gain and the equivalent output resistance vary as a function of line, load and output voltage. as the lo ad increases, the powertrain pole moves to higher frequency. as a result, the closed loop crossover frequency will be the highest at full load and lowest at minimum load. figure 24 show s a reference ac small-signal model. ? figure 24 ? prm48bh480[x]250a00 ac small signal model ifb: current feedback (remote sense operation) in remote sense operation, ifb is the input for the module output overcurrent protection an d current limit features. a voltage proportional to the powertrain output current must be applied to ifb in order for over current protection to operate properly. if the ifb voltage exceeds the ifb pin?s overcurrent protection threshold, the powertrain will st op switching. if the ifb voltage falls below the overcurrent pr otection threshold within t blank time, then the powertrain will i mmediately resume switching. otherwise a fault is detected. the current limit threshold for the ifb pin is set lower than the protection threshold. when the ifb pin average voltage exceeds the current limit threshold, an internal integrator will activate a clamp amplifier which overrides the modulator input maximum level. this causes th e powertrain to maintain a constant output current. the bandwidth of this current lim it integrator is significantly slower than that of the cont rol node input. therefore this current limit cannot be used in lieu of properly compensating the (external) control loop to avoid exceeding maximum current or power ratings for the device. v cn g cn c out_int + - i cn_low r cn + - r eq_out r eq_in v in + - c in_int
- 27 - prm48bh480 x 250a00 rev. 1.0 11/2012 design guidelines the prm48bh480[x]250a00 regulator is specifically designed to provide a controlled factor ized bus distribution voltage for powering downstream vtm transformer ? fast, efficient, isolated, low noise point-of-load (pol) converters. the prm48bh480[x]250a00 can be configured for two operating modes depending on the type of regulation required. in adaptive loop operation the r egulation circuitry is enabled within the device and regulates the voltage at the output terminals. the prm48bh480[x]250a00 has a programmable adaptive loop load line which can be used to compensate for downstream vtm output resistance allowing for precise point of load regulation without the need for remote sensing. in remote sense operation, the internal regulation circuitry is disabled and the voltage regulation circuitry is provided externally allowing for remote se nsing directly at the point of load. in certain applications remote sense operation can improve regulation accuracy, and allow for operating with high amounts of load capacitance and optimizing load transient response. operating mode selection the operating mode is selected through use of the trim pin. when the part is first enabled after v in is applied, the trim voltage is sampled. the trim pin has an internal pull up resistor to v cc_int , so unless external circuitry pulls the pin voltage lower, it will float up to v cc_int . if trim is pulled lower than 0.45v during the first startup after v in is applied, the part will be configured for remote sense / slave operation, where the internal voltage regulation circuitry is disabled. in this case, for all subsequent operation the part will output a voltage dependent on the share / control node voltage provided externally (either from an external regulation circuit or master prm). to configure the part for remo te sense or slave operation, connect the trim pin to sgnd . it is recommended to make this connection through a 0 ? jumper for troubleshooting purposes. if the sampled trim voltage is higher than 0.55v during the first startup after v in is applied, then the part will be configured for adaptive loop operation, and t he internal voltage regulation circuitry is enabled. the prm will output a voltage dependent on the trim voltage, and will remain in this mode for as long as v in is applied. to configure the part for adapt ive loop operation, leave the trim pin disconnected, or apply a voltage/resistance within the specified range. the operating mode is detected and latched during the first start up after v in is applied. this selection persists until v in is removed from the part, and is not changed by fault or disable events. changing the operat ing mode can only be done by removing v in . design guidelines (adaptive loop operation) in adaptive loop operation, the internal voltage control circuitry is enabled and the voltage at the output terminals is regulated. the part is nominally set to provide a fixed 48v output, and the trim pin can be used to adjust the output over the range of 20 v to 55 v. when used with a vtm, the al pin provides ability to program an adaptive loop load line to compensate for the output resistance (r out ) of a downstream vtm, while the vt pin provides temperature compensation to account for changes in the vtm r out over temperature. trim mode and output trim control (adaptive loop operation) in adaptive loop operation, during any start up and after enable transitions high, the trim pin voltage is sampled to determine if trim is active or inactive. if the sampled trim voltage is higher than 3.20v then the prm will disable trim. in this case, for all subsequent operation the output voltage will be programmed to the nominal output of 48v and the trim pin will be ignored during normal operation. if the sampled trim voltage is between 1.0 v and 3.10 v then the prm w ill activate trim mode and it will remain in this mode as l ong as the prm is operating. this selection persists until the prm is restarted with the enable pin, or due to fault auto-recovery.
- 28 - prm48bh480 x 250a00 rev. 1.0 11/2012 figure 25: trim connection the output as a function of v trim is defined by equation (1) for 1.00 v v trim 2.75 v, and allows for an output voltage ranging from 20v to 55v. the trim pin is pulled up internally to v cc_int thorough a 10 k ? resistor. v trim can be actively set with a dac that is ground referenced to sgnd. v trim can be passively set by connecting a resistor, r trim , from trim to sgnd such that the voltage divider made with v cc_int and the 10 k ? pull up yields the desired v trim . the formula for calculating this resistor is provided in equation (1a). ?20 ?????????????????????????????????????????????????? (1) ?????? ? ? _ ? _ _ ???? (1a) ? for 1.00 v v trim 2.75 v where v out_set is the desired output voltage the output voltage tranfer function saturates for applied trim voltages above approximately 2.75v as illustrated in figure 26 to prevent the output from bei ng driven above its rated output voltage. when trim is set lower than 1.00 v the output voltage is not specified and stable operation is not guaranteed. figure ? 26: ? prm ? v out ? vs. ? v trim ? when trim is enabled the voltage at this pin is sampled at 120 s intervals to determine the trim level. the output can be dynamically trimmed during normal operation, however it is not recommended to use this pin in an external analog feedback loop. refer to table 1 for a summary of the trim pin functionality and the recommended voltage/resistance that should be applied to this pin. trim pin function summary operating state v trim r trim detected and latched remote ? sense ? / ? slave ? operation ? <0.45v ? <1 ? k ?? after ? application ? of ? v in when ? enable ? first ? transitions ? high ? adaptive ? loop ? operation ? >0.55v [2] ? > ? 3 ? k ?? [2] ? after ? application ? of ? v in when ? enable ? first ? transitions ? high ? adaptive ? loop ? operation ? trim ? mode ? trim ? active ? v out ? = ? 20* ? v trim ? 1.00 ? v ? to ? 2.75 ? v ? 4.32 ? k ?? to ? 49.9 ? k ?? at ? every ? start ? up ? when ? enable ? transitions ? high ? trim ? inactive ? v out ? = ? 48v ? >3.2 ? v ? >10 ? m ?? table 1: trim pin function summary [2] it is not recommended to configure trim with a voltage less than 1.00v in adaptive loop operation vccint 10k trim mi c ro controller vt rim sgnd rtrim 0 10 20 30 40 50 60 0 10 20 30 40 50 60 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 trim pin resistor (k ? ) output voltage (v) trim pin voltage (v) prm v out vs v trim output ? voltage ? (v) at ? pin ? resistor ? (k ? ) unspecified operation recommended ? range
- 29 - prm48bh480 x 250a00 rev. 1.0 11/2012 adaptive loop compensation (adaptive loop operation) a factorized power system naturally has a dc load line associated with it since the regul ator stage (prm) is positioned before the isolation and voltage transformation stage (vtm.) consider for a moment a factorized power system that has the following parameters: ? v f ? = ? 40v ? ? k vtm =1/4 ? ? r out_vtm ? ? =10mohm ? @ ?? 25c ? at no load the output voltage at the load will be equal to 10v (v f ? k vtm ). with increasing load current, the output voltage at the load will drop at a rate proportional to the vtms r out . it should be noted that the r out has a positive temperature coefficient and so the dc load line changes with temperature. if the presence of this load line is acceptable for your application, then the prm can be configured by way of the trim pin alone. please refer to the trimming the output voltage section for details. in this case both the al and vt pins should be left open. if the presence of this load line is undesirable, the load line can be eliminated by way of the prm?s adaptive loop (al) engine. the al engine measures the output current of the prm and accordingly increases the output voltage of the prm in order to regulate the prm?s output re sistance to a fixed negative resistance, r ll_al , settable by way of the al pin. r ll_al should be sized to exactly cancel the r out of the vtm at 25c. the al engine is also able to account for the positive temperature coefficient of r out by way of its vt pin which will be explained shortly. ? figure 27: adaptive loop comp ensation illustration ? ? ? ? figure 28: prm-vtm adaptive loop example ? \ 3 \ 2 \ 1 0 1 2 3 0 20406080100 output voltage %difference from nominal (%) load current (%) prm and vtm output voltage adaptive loop comensation example vtm ? vout ? (uncompensated) prm ? vout vtm ? vout ? (regulated) compensated vtm output adaptive loop compensation brings output into regulation vtm startup pulse adaptive loop temperature feedback 36v to 75v vf: 20v to 55v lf ral rtrim cf cout cin sgnd sgnd gnd on/off control vin vout se c_gnd trim al +in -in +out -out vc ifb vt ref/ ref_en vaux share/ control node enable sgnd prm sgnd +in -in +out -out vc pc primary secondary isol at i on boundry tm vtm v in 38v to 55v
- 30 - prm48bh480 x 250a00 rev. 1.0 11/2012 setting the adaptive loop load line (adaptive loop operation) to determine an appropriate value for the compensation slope (r ll_al ) it helps to reflect the vtm?s output resistance to the input side of the vtm. a resi stance on the output side of the vtm is scaled by the vtms transformer ratio (k vtm ) squared as defined by equation (2): _ _ __ ? (2) where r out_vtm is the vtm output resistance at 25c k vtm is the vtm transformer ratio v in /v out for our hypothetical vtm from above (with k vtm = 1/4 and r out_vtm = 10m ? ) the output resistance reflected over to the input would be equal to 160 m ? . for this example, r ll_al should be set to -160 m ? to approximately cancel at 25c the inherent load line from the vtm. r ll_al is set by the voltage difference between the al pin and sgnd pin, v al , per the following formula: r _ v ? 1.0 ? /v ???? ??????????? (3) ? v al 3.10v where v al is the voltage on the al pin v al is sampled by a 10-bit adc, whose input is connected to v cc_int through a 10 k ? pull up resistor. this pull up disables the al engine when the al pin is left open. v al can be actively set with a dac that is ground referenced to sgnd. v al can be passively set by connecting a resistor, r al , from al to sgnd such that the voltage divider made with v cc_int and the 10 k ? pull up yields the desired v al . the formula for calculating this resistor is provided in equation (4). ? _ ? ? ? ???????????? (4) ? figure 29: al connections similar to trim, al is sampled during every start up to determine if the adaptive loop load line is enabled or disabled. if the al pin is allowed to pull up to 3.20v or higher during start up, then then the prm will disa ble the adaptive loop load line as long as the prm remains oper ating. in this case, for all subsequent operation the output voltage w ill be remain at the set voltage, and the al pin will be ignored. this selection persists until the prm is restarted with the enable pin, or due to fault auto-recovery. when al is enabled, the voltage at this pin is sampled at 120 s intervals to determine the load line. the load line can be adjusted during normal operat ion, however it is not recommended to use this pin in an external analog feedback loop. adaptive loop temperature compensation (adaptive loop operation) by connecting the vt pin of the prm to the vtm?s tm pin, the prm is able to monitor the internal temperature of the vtm. knowing the vtm?s internal te mperature and the temperature coefficient of the vtm?s r out , which is preprogrammed into the prm?s microcontroller, the al engine is able to scale the nominal value of r ll_al (set by the al pin) to track the vtm?s r out over temperature. in this wa y the output resistance of the prm can be tuned to cancel the output resistance of the vtm with the addition of a single resistor across the al pin and a connection of the vtm?s tm pin to the prm?s vt pin. the vtm tm voltage is equal to the vtm internal sensed temperature in kelvin divided by 100. for a temperature range of -55 c to 125 c the tm voltage will range from 2.18 v to 3.98 v. the adaptive loop temperature compensation is pre-programed into the internal microcontroller and is 0.3 %/ c assuming the vt pin is connected to the tm pin of a compatible vtm the tm pin has an internal pull down to sgnd, and temperature compensation is disabled for vt voltages less than 1.9v. to disable temper ature compensation, leave the vt pin unconnected and open circuit. when disabled, the temperature defaults 25 c. val sgnd vccint 10k al mi c ro controller ral
- 31 - prm48bh480 x 250a00 rev. 1.0 11/2012 figure 30: vt connections figure 31: adaptive loop temp erature compensation illustration the discussion thus far only considered the case where the al engine is used to compensate for the r out of the vtm. the al engine can be more generally used to account for distribution resistances in both the factor ized bus and the vtm?s output distribution bus. for more information on how to apply the al engine towards this end please contact vicor?s applications engineering department. stability considerations and external capacitance (adaptive loop operation) in adaptive loop operation, the internal voltage regulation is enabled which has a pre-determined, fixed compensation network. the compensation is designed to be stable over a fixed set of operating and load conditions including load capacitance. besides internal output capacitor s, external output capacitors also contribute to the closed loop frequency response, thus should be identified and understood, in order to maintain the control loop stability. this includ es capacitance placed directly on the prm output, as well as capacitance on the output of any downstream vtm (if used) reflected to its input. figure 32 illustrates the requirements for external capacitors of both the capacitance and esr value. as shown in figure 32 (a), the maximum capacitance value of ceramic capacitor is 25 f, and the capacitance of a combination of ceramic and electrotype capacitors needs to be less than 47 f. as shown in figure 32 (b) and (c), the esr value of electrotype capacitors needs to be between 0.1 ? and 1.0 ? ; the esr value of ceramic capacitors needs to be between 2 m ? and 200 m ? . c el (uf) c cer (uf) 25 47 c cer + c el < 47 22 c cer 25 esr (ohm) esr el 0.1 esr 1 1 0.1 esr (ohm) esr cer 0.02 esr 0.2 0.2 0.02 (a) maxium ? capacitance ? limits ?????????????????????? (b) ? esr el ? requirements ?????????????? (c) ? esr cer ? requirements ? figure 32: output capacitance limits vt 20k 60.4k sgnd mi cro co n tro ller vt m t m 2.18v to 3.98v (-55c to 125c) \ 3 \ 2 \ 1 0 1 2 3 0 20406080100 output voltage %difference from nominal (%) load current (%) prm and vtm output voltage adaptive loop with temperature compensation vtm ? vout: ? 25c ? (uncompensated) vtm ? vout ? (regulated) vtm ? vout: ?\ 55c ? (uncompensated) vtm ? vout: ? 100c ? (uncompensated) prm ? vou: ? 25c ? (vt ? = ? 2.98v) prm ? vout: ?\ 55c ? (vt ? = ? 2.18v) prm ? vout: ? 100c ? (vt ? = ? 3.73v) compensated vtm output compensation slope increases with temperature based on vt feedback vtm rout increases with temperature
- 32 - prm48bh480 x 250a00 rev. 1.0 11/2012 current limit (adaptive loop operation) in adaptive loop operation, the cu rrent limit is controlled by the internal microcontroller. the current limit approximates a ?brick-wall? limit where the out put current is prevented from crossing the current limit thre shold by reducing the output voltage. the current limit threshold is pre-programmed into the internal microcontroller and cannot be changed externally. when the internal sensed current crosses the current limit threshold, the current limit will be activated after the detection time t lim_supv . once activated, the microcontroller will reduce the error amplifier reference vo ltage (represented by ref) in order to maintain the output curr ent at the limit value. current limit is able to reduce the output down to v out_uvp , below which the device will shut down do to output under voltage protection. soft start timing and start up (adaptive loop operation) in adaptive loop operation, the prm has an internal soft start sequence which is initiated at every start up. this allows the prm to start into fully discharged load capacitance. the soft start sequence ramps the out put by modulating the error amplifier reference voltage (ref). the result is that the prm output will rise at a controlled rate until the final voltage setpoint is reached. the total ramp time is typically 1.8ms independent of the output trim level. this soft start ramp time is preprogrammed into the microcontroller and cannot be changed externally. load transient response (adaptive loop operation) in adaptive loop operation, response time is dependent on the internal compensation. when the adaptive loop load line is disabled, the prm output voltage w ill recover to the initial set value as illustrated in figure 33 and figure 34. figure 33: prm example 10% to 100% load transient response, adaptive loop load line disabled figure 34: prm example 100% to 10% load transient response, adaptive loop load line disabled when the adaptive loop load line is enabled, the voltage will recover to the value determined by the set point and adaptive loop load line settings as illustrated in figure 35. figure 35: prm example 10% to 100% load transient response, adaptive loop load line enabled, v al = 1.25v actual response times are model de pendent and will change based on the load step magnit ude, load capacitance and operating conditions. because the compensation is fixed internally the load transient response cannot be altered for adaptive loop operation. in order to improve the load transient response performance, the part can be configured for remote sense operation with an external voltage control loop opt imized for the specific intended operating conditions. remote sense operation is described in a later section.
- 33 - prm48bh480 x 250a00 rev. 1.0 11/2012 arrays (adaptive loop / slave operation) in adaptive loop operation a master-slave configuration is used for arrays. up to 5 prms of the same type may be placed in parallel to expand the power capacity of the system. one prm is designated as the master and contains the active control loop which considers control pin inputs and drives share. the other prms list en to share and act as slave powertrains only. the following high-level guidelines must be followed in order for the resultant system to start up and operate properly, and to avoid overstress or exceeding any absolute maximum ratings. ? one prm must be designated as a master through configuring the trim pin voltage within the recommended range. ? all other prms must be designated as slave prms by tying trim pins to sgnd. it is recommended to make this connection through a 0 ? jumper for troubleshooting purposes. ? all prms in the array must be powered from a common power source so that the input voltage to each prm is the same. the in pins of all prms must be connected together. ? an independent fuse for each prm +in connection is required to maintain safety certifications (see fusing section). ? an independent inductor for each prm +in connection is recommended when used in an array, to control circulating currents among the prm inputs and reduce the impact of beat frequencies. ? mismatches in both inductance, and resistance from the common power source to each prm should be minimized. ? enable pins must be connected together for start up synchronization and proper faul t response of the array. ? share pins must be connected together to enable sharing. the bandwidth requirements of share are low enough that the bus can be considered a lumped element, rather than a transmission line, and so star connections to the master prm with stubs, as well as daisy chain connectio ns are permitted. ? the resistances between slave unit share pins and the master?s should be well matched, to avoid introducing additional sharing mismatches. the share bus should not be routed under any prm. share bus parasitic capacitance to +in or +out should be minimized. ? sgnd of the master prm is the reference for all control loop functions. the sgnd pins of each slave prms should be connected to the sgnd reference node on the board through a 1 ? resistor. ? when operating within an array, the master prm is rated for full power while the slave prms are de-rated to the array rated power and current values provided for slave operation(p out_array ,i out_array ). the number of prms required to achieve a given array capacity must consider these de-ratings to avoid overstressing any prm in the array. ? ? adaptive loop design procedures above will hold for an array, in general, although some parameters must be scaled against the number of prms in the system. ? arrays of more than 5 prms may be possible through use of external circuitry. please c ontact vicor applications for assistance with array sizing above 5 units.
- 34 - prm48bh480 x 250a00 rev. 1.0 11/2012 design guidelines (remote sense operation) in remote sense operation, the prm48bh480[x]250a00 is an intelligent powertrain module designed to fully exploit external output voltage feedback and current sensing sub-circuits. these two external circuits are illustrated in figure 36, which shows an example of the prm in a standalone application with local voltage feedback and high side current sensing. in general, these circuits include a precision voltage reference, an operational amplifier which provides closed loop feedback compensation, and a high side current sense circuit which includes a shunt and current sense ic. the following design procedures refer to the circuit shown in figure 36. setting the output voltage level (remote sense operation) the output voltage setpoint is a function of the voltage reference and the output voltage sense ratio. with reference to figure 36, r1 and r2 form the output voltage sensing divider which provides the scaled output voltage to the negative input of the error amplifier; a dedicated reference ic provides the reference voltage to the positive input of the error amplifier. under normal operation, the error amplifier will keep the voltages at the inverting and non-inverting inputs equal, and therefore the output voltage is defined by: 2 2 1 r r r v v ref out ? ? ? (5) note that the component r1 will also factor into the compensation as described in a later section. it is important to apply proper slew rate to the reference voltage rise when the control loop is initially enabled. the recommended range for reference rise time is 1 ms to 9 ms. the lower rise time limit will ensure optimized modulator timing performance during start up, and to allow the current limit feature (through ifb pin) to fu lly protect the device during power-up. the upper rise time limit is needed to guarantee a sufficient factorized bus voltage is provided to any downstream vtm input before the end of the vc pulse. setting the output current limit and overcurrent protection level (remote sense operation) in remote sense operation, t he internal current sensing is disabled, and an external curr ent sense amplifier must be implemented to provide feedback to the ifb pin. the current limit and overcurrent protection set points are linked, and scale together against the current sense shunt, and the gain of the current sense am plifier. the output of the current sense ic provides the ifb voltage which has v ifb_il and v ifb_oc thresholds for the two functions respectively. the set points are therefore defined by: cs s il ifb il g r v i ? ? _ (6) and cs s oc ifb oc g r v i ? ? _ (7) where g cs is the gain of the current sense amplifier.
- 35 - prm48bh480 x 250a00 rev. 1.0 11/2012 figure 36: remote sense example vs pr +in -in if re sg -out +out f1 i sense ic vref + - c2 c1 r3 r1 r2 vref ic vref c in_int c out_int c out_ext c in_ext r s vaux control node ifb ref_en sgnd prm tm regulator
- 36 - prm48bh480 x 250a00 rev. 1.0 11/2012 control loop compensation requirements (remote sense operation) in order to properly compensate the control loop, all components which contribute to the closed loop frequency response should be identified and understood. figure 24 shows the ac small signal model for the module. modulator dc gain g cn and powertrain equivalent resistance r eq_out are shown. these modeling parameters will support a design cut- off frequency up to 50khz. standard bode analysis should be used for calculating the error amplifier compensation and analyzing the closed loop stability. the recommended stabilit y criteria ar e as follows: 1) phase margin > 45o : for the closed loop response, the phase should be greater than 45o where the gain crosses 0db. 2) gain margin > 10db : the closed loop gain should be lower than -10db where the phase crosses 0o. 3) gain slope = -20db/decade : the closed loop gain should have a slope of -20db/decade at the crossover frequency. the compensation characteristics must be selected to meet these stability criteria. refer to figure 37 for a local sense, voltage-mode control example ba sed on the configuration in figure 36. in this example, it is assumed that the maximum crossover frequency (f cmax ) has been selected to occur between b and c. type-2 compensation (curve ijkl) is sufficient in this case. the following data must be gathered in order to proceed: ? modulator gain g cn : see figures 18, 19, 20 ? powertrain equivalent resistance r eq : see figures 18, 19, 20 ? internal output capacitance: see figure 13 ? external output capacitance value in the case of ceramic capacitors, the esr can be considered low enough to push the associated zero well above the frequency of interest. applications with high esr capacitor may require a different type of compensation, or cascade control. the system poles and zeros of the closed loop can then be defined as follows: ? powertrain pole, assuming the external capacitor esr is negligible: load out eq load out eq c r r r r r ext out ? ? ?? _ _ _ ? main ? pole ? frequency: ? ?? ext out int out load out eq load out eq p c r r r r _ _ _ _ c 2 1 f ? ? ? ? ? ? ? compensation ? mid \ band ? gain: ? 1 3 mb r r log 20 g ? (8) ? compensation ? zero: ? 1 3 1 z c r 2 1 f ? ? ? (9) ? compensation ? pole: ? 2 1 2 1 3 2 2 1 f c c c c r p ? ? ? ? ? and for f p2 >>f z1 (c 1 + c 2 c 1 ): 2 3 2 2 1 f c r p ? ? ? ? (10)
- 37 - prm48bh480 x 250a00 rev. 1.0 11/2012 midband gain design: r1,r3 (remote sense operation) with reference to figure 37: curve abc is the: ? minimum ? output ? voltage ? in ? the ? application ? ? maximum ? input ? voltage ? expected ? in ? the ? application ? ? maximum ? load ? prm open loop response, and is where the maximum crossover frequency occurs. in order for the maximum crossover frequency to occur at the design choice f cmax , the compensation gain must be equal and opposite of the powertrain gain at this freque ncy. for stability purposes, the compensation should be in the mid-band (j-k) at the crossover. using equation (8), the mid-band gain can be selected appropriately. compensation zero design :c1 (remote sense operation) : with reference to figure 37: curve efg is the: ? maximum ? output ? voltage ? in ? the ? application ? ? minimum ? input ? voltage ? expected ? in ? the ? application ? ? minimum ? load ? in ? the ? application ? prm open loop response, and is where the minimum crossover frequency f cmin occurs. based on stability criteria, the compensation must be in the mid-band at the minimum crossover frequency, therefore f cmin will occur where efg is equal and opposite of g mb . c1 can be selected using equation (9) so that f z1 occurs prior to f cmin . high frequency pole design: c2 (remote sense operation): using equation (10), c2 should be selected so that f p2 is at least one decade above f cmax and prior to the gain bandwidth product of the operational amplifier (10mhz for this example). for applications with a higher desired crossover frequency the use of a high gain bandwidth product amplifier may be necessary to ensure that the real pole can be set at least one decade above the maximum crossover frequency. figure 37 ? reference asymptotic bode pl ot for the considered system open loop gain vs. frequency -40 -20 0 20 40 60 80 frequency, log scale (y-intercept is application specific) gain (db) prm open loop max load a b e f i j k l compensation gain a pplication's op-amp gbw c g f cmax f cmin prm open loop min load
- 38 - prm48bh480 x 250a00 rev. 1.0 11/2012 arrays (remote sense operation) in remote sense operation up to 10 prms of the same type may be placed in parallel to expand the power capacity of the system. all prms within the array are configured for remote sense operation and are driven by an external control circuit which considers the control inputs and drives the control node bus. the following high-level guidelines must be followed in order for the resultant system to start up and operate properly, and to avoid overstress or exceeding any absolute maximum ratings. ? all prms must be configured for remote sense operation by tying trim pins to sgnd. it is recommended to make this connection through a 0 ? jumper for troubleshooting purposes. ? all prms in the array must be powered from a common power source so that the input voltage to each prm is the same. ? an independent fuse for each prm +in connection is required to maintain safety certifications (see fusing section). ? an independent inductor for each prm +in connection is recommended when used in an array, to control circulating currents among the prm inputs and reduce the impact of beat frequencies. ? mismatches in both inductance, and resistance from the common power source to each prm should be minimized. ? enable pins must be connected together for start up synchronization and proper faul t response of the array. ? reference supply to the control loop voltage reference and current sense circuitry must be enabled when all modules? ref_en pins have reached their operational voltage levels. ? a single external control circuit must be implemented as described in the remote sense operation design guidelines. the control circuit should drive the control node bus. ? control node pins must be connected together to enable sharing. the bandwidth requirements of control node are low enough that the bus can be considered a lumped element, rather than a transmission line, and so star connections as well as daisy chain connectio ns are permitted. ? each prm must have its own local current shunt and current sense circuitry to drive its ifb pin. ? the resistances between control node pins should be well matched, to avoid introducing additional sharing mismatches. the control node bus should not be routed under any prm. parasitic capacitance to +in or +out should be minimized. ? one prm should be designated to provide the sgnd reference, vaux, and ref_en voltages for the external circuitry. ? the sgnd pins of all other prms should be connected to the sgnd reference node on the board through a 1 ? resistor. ? when operating within an array, the prms are de- rated to the array rated power and current values provided for remote sense operation (p out_array , i out_array ). the number of prms required to achieve a given array capacity must co nsider these de-ratings to avoid overstressing any prm in the array. ? ? when using vaux to power ex ternal circuitry, total current draw including control node sink currents must be taken into account to ensure the maximum vaux current is not exceeded. arrays of more than 5 prms may require additional circuitry to provide the required source current. contact vicor applications engineering for more information. ?
- 39 - prm48bh480 x 250a00 rev. 1.0 11/2012 design guidelines (general operation) the following guidelines are general guidelines that apply to any mode of operation. fpa system considerations there are a few system level design considerations that should be carefully considered when using a prm and vtm to implement a factorized power architecture (fpa) system the vc pin of the prm should be directly connected to the vc pin of the vtm. the prm and vtm coordinate the soft start sequence of the fpa system through this connection. if the vc pins are not connected the vtm will not start up. when the prm is ready to start up, it applies a voltage on vc, which enables and powers the vtm?s powertrain. the prm then proceeds to ramp up its output voltage. after approximately 10ms, vc returns to 0v and the vtm can then derive power directly from the factorized bus provided that the factorized bus voltage is above the minimum specified vtm operating input voltage when the vc pulse expires. all vtm faults latch the vtm power train off. input power to the system as a whole must be recycled or the prm should be disabled and enabled by way of its enable pin in order to restart the system. it is re commended that the voltage on the factorized bus return to zero before the prm is re-enabled. otherwise the soft start of t he system may be compromised. a rl filter should be placed between the prm and vtm to locally isolate switching ripple currents that can interfere with module operation. it is important that the inductance have an impedance that is much greater than that of the prm output capacitance and vtm input capacitance at the switching frequencies of the devices. a resistor should be placed in shunt to this inductor to dampen the resultant lc tank. for most cases 100nh in parallel with 10 ? is sufficient to isolate the switching ripple currents. verifying stability : a load step transient response can be used in order to estimate stability. figure 38 illustrates an example of a load step response. equation (11) can be used to predict the phase margin based on the ratio of the ?kick? to ?droop? (as defined in fig. 38). v out i out d k v out i out d k time time time time (a) without ? adaptive ? loop ??????????????????????????????? (b) ? with ? adaptive ? loop ? figure 38 ? load step response example and ?droop? vs. ?kick? definition. (a) with adaptive lo op; (b) without adaptive loop. 2 2 2 ln ln 100 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? d k d k m (11) burst mode operation : at light loads, the prm will ope rate in a burst mode due to minimum timing constraints. an example burst operation waveform is illustrated in figure 39. for very light loads, and also for higher input voltages, the minimum time power switching cycle from the powertrain will exceed the power required by the load. in this case the error amplifier will periodically driv e share/conrol node below the switching threshold in order to maintain regulation. switching will cease momentarily until the error amplifier once again drives share/control node voltage above the threshold. figure 39 ? light load burst mode of operation
- 40 - prm48bh480 x 250a00 rev. 1.0 11/2012 note that during the bursts of switching, the powertrain frequency is constant, but the number of pulses as well as the time between bursts is variabl e. the variability depends on many factors including input voltage, output voltages, load impedance, and error amplif ier output impedance. in burst mode, the gain of the share/control node input to the plant which is modeled in the previous sections is time varying. therefore the small si gnal analysis cannot be directly applied to burst mode operation. input and output filter design figures 14 and 15 provide the total input and output charge per cycle, as well as switching frequency, of the prm at full load under various input and output voltages conditions. figure 13 provides the effectiv e internal capacitance of the module. a conservative estima te of input and output peak- peak voltage ripple at nominal line and trim is provided by equation (12): ext int sw fl tot c c f i q v ? ? ? ? ? 4 . 0 (12) q tot is the total input (fig. 14) or output (fig. 15) charge per switching cycle at full load, while c int is the module internal effective capacitance at the considered voltage (fig. 13) and c ext is the external effective c apacitance at the considered voltage. input filter stability the prm can provide very high dynamic transients. it is therefore very important to ve rify that the voltage supply source as well as the interconnecting line are stable and do not oscillate. for this purpose, the converter dynamic input impedance magnitude in eq r _ is provided in figures 21, 22, 23. it is recommended to provide adequate design margin with respect to the stability condition s illustrated in the previous sections. inductive source and local, external input decoupling capacitance with negligible esr (i.e.: ceramic type) the voltage source impedance can be modeled as a series r line l line circuit. the high performance ceramic decoupling capacitors will not significantly damp the network because of their low esr; therefore in order to guarantee stability the following conditions must be verified: in eq ext in int in line line r c c l r _ _ _ ) ( ? ? ? (13) in eq line r r _ ?? (14) it is critical that the line source impedance be at least an octave lower than the converter?s dynamic input resistance (14). however, r line cannot be made arbitrarily low otherwise equation (13) is violated and the system will show instability, due to under-damped rlc input network. inductive source and local, external input decoupling capacitance with significant r cin_ext esr (i.e.: electrolytic type) in order to simplify the analysis in this case, the voltage source impedance can be modeled as a simple inductor l line . notice that, the high performance ceramic capacitors c in_int within the prm should be included in the external electrolytic capacitance value for this purpos e. the stability criteria will be ext in c in eq r r _ _ ? (15) in eq c ext in line r r c l ext in _ _ _ ? ? (16) equation (16) shows t hat if the aggregate esr is too small ? for example by using very high quality input capacitors (c in_ext ) ? the system will be under-damped and may even become destabilized. again, an oc tave of design margin in satisfying (15) should be considered the minimum. layout considerations application note an:005 details board layout recommendations using v?i chip components, with details on good power connections, reducing emi, and shielding of control signals and techniques to reference them to sgnd. avoid routing control signals (en able, trim, al etc.) directly underneath the prm. it is critical that all control signals (aside from vc and vt) are referenced to sgnd, both for routing and for pull-down and bypassing purposes. vc and vt provide control and feedback from a vtm, and must be referenced to ? out of the prm (-in of the vtm) sgnd is connected to ?in internally to the prm. sgnd should not be tied to any other ground in the system.
- 41 - prm48bh480 x 250a00 rev. 1.0 11/2012 input fuse recommendations a fuse should be incorporated at the input to each prm, in series with the +in pin. a 10a or smaller input fuse (littlefuse ? nano 2? 451/453 series) is required to safety agency conditions of acceptability. al ways ascertain and observe the safety, regulatory, or other agency specifications that apply to your specific application. thermal considerations v?ichip tm products are multi-chip modules whose temperature distribution varies greatly for ea ch part number as well as with the input / output conditions, thermal management and environmental conditions. ma intaining the top of the prm48bh480[x]250a00 case to less than 100oc will keep all junctions within the v?i chip module below 125oc for most applications. the percent of total heat dissipated through the top surface versus through the j-lead is entirely dependent on the particular mechanical and thermal environment. the heat dissipated through the top surf ace is typically 60%. the heat dissipated through the j-lead ont o the pcb board surface is typically 40%. use 100% top surface dissipation when designing for a conservative cooling solution. it is not recommended to use a v?i chip module for an extended period of time at full load without proper heat sinking.
- 42 - prm48bh480 x 250a00 rev. 1.0 11/2012 product outline drawing and reommended land pattern
- 43 - prm48bh480 x 250a00 rev. 1.0 11/2012 revision history revision date description page number(s) 1.0 11/12/2012 final approved datasheet for initial release all
- 44 - prm48bh480 x 250a00 rev. 1.0 11/2012 vicor?s comprehensive lin e of power solutions includes high density ac- dc and dc-dc modules and accessory components, fully configurable ac-dc and dc-dc power suppli es, and complete custom power systems. information furnished by vicor is believed to be accurate and r eliable. however, no responsibility is assumed by vicor for its use. vicor makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication. vicor reser ves the right to make changes to any products, specifications, and product descripti ons at any time without notice. information published by vi cor has been checked and is believed to be accurate at the time it was prin ted; however, vicor assumes no responsibility for inaccuracies. testing and other quality controls are used to the extent vicor deems necessary to support vicor?s product warranty. except where mandated by go vernment requirements, testing of all par ameters of each product is no t necessarily performed. specifications are subject to change without notice. vicor?s standard terms and conditions all sales are subject to vicor?s standard terms and conditions of sale, which are available on vicor?s webpage or upon request. product warranty in vicor?s standard terms and conditions of sale, vicor warrants that its products are free from non-conformity to its standard specifications (the ?express limited warranty?). this warranty is extended only to the original buyer for the period expiring two (2) years after t he date of shipment and is not transferable. unless otherwise expressly stated in a written sal es agreement signed by a duly authorized vicor signatory, vicor disclaims all representations, liabi lities, and warranties of any kind (whether arising by implication or by operation of law) with respect to the products, i ncluding, without limitation, any warranties or representations as to merchantability, fitness for particular purpose, infringement of any patent, copyright, or other intellectual property right, or any other matter. this warranty does not extend to products subjected to misuse, a ccident, or improper application, maintenance, or storage. vico r shall not be liable for collateral or consequential damage. vicor disclaims any and all liability arising out of the application or use of any product or circuit and assumes no liability for applications assistance or buyer pr oduct design. buyers are responsible for their products and applica tions using vicor products and components. prior to using or distributing any pr oducts that include vicor components, buyers should provide adeq uate design, testing and operating safeguards. vicor will repair or replace defective products in accordanc e with its own best judgment. for service under this warranty, the buyer must contact vicor to obtain a return material authorization (rma) number and shipping instructions. products returned without prior author ization will be returned to the buyer. the buyer will pay all charges incurred in returning the product to the factory. vicor will pay all re shipment charges if the product was defective within the terms of this warranty. life support policy vicor?s products are not authorized for use as critica l components in life su pport devices or systems without the express prior written approval of the chief executive officer and general counsel of vicor corporation. as used herein, life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the us er. a critical component is any component in a life support devi ce or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness. per vicor terms and conditions of sale, the user of vicor produc ts and components in life support applications assumes all risks of such use and indemnifies vicor against all liability and damages. intellectual property notice vicor and its subsidiaries own intellectual property (includi ng issued u.s. and foreign patent s and pending patent applications ) relating to the products described in this data sheet. no license, whether express, implied, or arising by estoppel or otherwise, to any intel lectual property rights is granted by this document. interested parties should contact vicor's inte llectual property department. the products described on this data sheet are protec ted by the following u.s. patents numbers: 5,945,130; 6,403,009; 6, 710,257; 6,911,848; 6,930,89 3; 6,934,166; 6,940,013; 6,969,909; 7,038,917; 7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,84 4; d496,906; d505,114; d506,438; d509,472; and for use under 6,975,098 and 6,984,965. vicor corporation 25 frontage road andover, ma, usa 01810 tel: 800-735-6200 fax: 978-475-6715 email customer service: custserv@vicorpower.com technical support: apps@vicorpower.com

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